Monday, November 22, 2010
Thursday, November 18, 2010
Using libcap on CentOS 5
1. download libcap source from tcpdump.org
2. install it
2.1. yum install flex
2.2. download byacc from http://invisible-island.net/byacc/byacc.html
2.3. install byacc
3. then compile a sample program will be OK. But when running it, may got an error saying cannot find libcap.so.1. To solve this, use following:
set /usr/local/lib
/usr/lib
into /etc/ld.so.conf and then execute ldconfig command.
2. install it
2.1. yum install flex
2.2. download byacc from http://invisible-island.net/byacc/byacc.html
2.3. install byacc
3. then compile a sample program will be OK. But when running it, may got an error saying cannot find libcap.so.1. To solve this, use following:
set /usr/local/lib
/usr/lib
into /etc/ld.so.conf and then execute ldconfig command.
Wednesday, November 17, 2010
Debugging with GDB
http://davis.lbl.gov/Manuals/GDB/gdb.html#SEC_Top
Howto: GDB Remote Serial Protocol
Writing a RSP Server
http://www.embecosm.com/appnotes/ean4/embecosm-howto-rsp-server-ean4-issue-2.html
GDB Internals
gdb stub:
http://sca.uwaterloo.ca/coldfire/gcc-doc/docs/porting_4.html
Howto: GDB Remote Serial Protocol
Writing a RSP Server
http://www.embecosm.com/appnotes/ean4/embecosm-howto-rsp-server-ean4-issue-2.html
GDB Internals
gdb stub:
http://sca.uwaterloo.ca/coldfire/gcc-doc/docs/porting_4.html
Tuesday, November 16, 2010
SWITCH FROM REAL MODE TO PROTECTED MODE
http://blog.csdn.net/pengyang/archive/2009/03/10/3977909.aspx
http://blog.sina.com.cn/s/blog_414c0121010005o3.html
http://blog.chinaunix.net/u3/95743/showart.php?id=2286642
Intel CPU manual, 3A, chapter 9.9.1
1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI interrupts can be disabled with external circuitry. (Software must guarantee that no exceptions or interrupts are generated during the mode switching operation.)
2. Execute the LGDT instruction to load the GDTR register with the base address of the GDT.
3. Execute a MOV CR0 instruction that sets the PE flag (and optionally the PG flag) in control register CR0.
4. Immediately following the MOV CR0 instruction, execute a far JMP or far CALL instruction. (This operation is typically a far jump or call to the next instruction in the instruction stream.)
5. The JMP or CALL instruction immediately after the MOV CR0 instruction changes the flow of execution and serializes the processor.
http://blog.sina.com.cn/s/blog_414c0121010005o3.html
http://blog.chinaunix.net/u3/95743/showart.php?id=2286642
Intel CPU manual, 3A, chapter 9.9.1
1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI interrupts can be disabled with external circuitry. (Software must guarantee that no exceptions or interrupts are generated during the mode switching operation.)
2. Execute the LGDT instruction to load the GDTR register with the base address of the GDT.
3. Execute a MOV CR0 instruction that sets the PE flag (and optionally the PG flag) in control register CR0.
4. Immediately following the MOV CR0 instruction, execute a far JMP or far CALL instruction. (This operation is typically a far jump or call to the next instruction in the instruction stream.)
5. The JMP or CALL instruction immediately after the MOV CR0 instruction changes the flow of execution and serializes the processor.
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